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MC74HC4040A 12-Stage Binary Ripple Counter
High-Performance Silicon-Gate CMOS
The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.
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16
16 1
PDIP-16 N SUFFIX CASE 648
MC74HC4040AN AWLYYWW 1 16
16 1
* * * * * * *
SO-16 D SUFFIX CASE 751B 1
HC4040A AWLYWW
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAM
9 7 6 5 Clock 10 3 2 4 13 12 14 15 1 Reset 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
16 TSSOP-16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week HC40 40A ALYW
16 1
FUNCTION TABLE
Clock Reset L L H Output State No Charge Advance to Next State All Outputs Are Low
X
ORDERING INFORMATION
Device MC74HC4040AN MC74HC4040AD Q1 9 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel
Pin 16 = VCC Pin 8 = GND Q8 13 Q9 12 Reset Clock 11 10
VCC 16
Q11 15
Q10 14
MC74HC4040ADR2 MC74HC4040ADT MC74HC4040ADTR2
Pinout: 16-Lead Plastic Package (Top View)
1 Q12 2 Q6 3 Q5 4 Q7 5 Q4 6 Q3 7 Q2 8 GND
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 2
Publication Order Number: MC74HC4040A/D
MC74HC4040A
IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
IIII I I I I IIIIIIIIIIIIIIIIIIIII II IIII II IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 0 + 125 1000 600 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH
Parameter
Condition
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0
Guaranteed Limit -55 to 25C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 85C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 125C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.20 3.70 5.20 0.1 0.1 0.1 V Unit V
Minimum High-Level Input Voltage
Vout = 0.1V or VCC -0.1V |Iout| 20A
VIL
Maximum Low-Level Input Voltage
Vout = 0.1V or VCC - 0.1V |Iout| 20A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20A Vin =VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA
V
3.0 4.5 6.0 2.0 4.5 6.0
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| 20A
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MC74HC4040A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Condition Vin = VIH or VIL |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA VCC V 3.0 4.5 6.0 6.0 6.0 Guaranteed Limit -55 to 25C 0.26 0.26 0.26 0.1 4 85C 0.33 0.33 0.33 1.0 40 125C 0.40 0.40 0.40 1.0 160 A A Unit
Iin ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Vin = VCC or GND Iout = 0A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 10 15 30 50 96 63 31 25 45 30 30 26 69 40 17 14 75 27 15 13 10 85C 9.0 14 28 45 106 71 36 30 52 36 35 32 80 45 21 15 95 32 19 15 10 125C 8.0 12 25 40 115 88 40 35 65 40 40 35 90 50 28 22 110 36 22 19 10 Unit MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q1* (Figures 1 and 4)
ns
tPHL
Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4)
ns
tPLH, tPHL
Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 4)
ns
Cin
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: VCC = 2.0 V: tP = [93.7 + 59.3 (n-1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n-1)] ns VCC = 3.0 V: tP = [61.5 + 34.4 (n-1)] ns VCC = 6.0V: tP = [24.4 + 12 (n-1)] ns Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 31 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MC74HC4040A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol trec Parameter Minimum Recovery Time, Reset Inactive to Clock (Figure 2) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit -55 to 25C 30 20 5 4 70 40 15 13 70 40 15 13 1000 800 500 400 85C 40 25 8 6 80 45 19 16 80 45 19 16 1000 800 500 400 125C 50 30 12 9 90 50 24 20 90 50 24 20 1000 800 500 400 Unit ns
tw
Minimum Pulse Width, Clock (Figure 1)
ns
tw
Minimum Pulse Width, Reset (Figure 2)
ns
tr, tf
Maximum Input Rise and Fall Times (Figure 1)
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS Clock (Pin 10) OUTPUTS Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
Negative-edge triggering clock input. A high-to-low transition on this input advances the state of the counter.
Reset (Pin 11)
Active-high outputs. Each Qn output divides the Clock input frequency by 2N.
Active-high reset. A high level applied to this input asynchronously resets the counter to its zero state, thus forcing all Q outputs low.
SWITCHING WAVEFORMS
tf Clock 90% 50% 10% tw 1/fMAX tPLH Q1 90% 50% 10% tTLH tTHL tPHL tr VCC GND Reset tPHL Any Q 50% Clock trec tw 50% GND 50% GND VCC VCC
Figure 1.
Figure 2.
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MC74HC4040A
SWITCHING WAVEFORMS (continued)
TEST POINT VCC Qn 50% GND tPLH Qn+1 50% tPHL DEVICE UNDER TEST OUTPUT CL*
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
Q1 9
Q2 7
Q3 6
Q10 14
Q11 15
Q12 1
Clock
10
C
Q
C
Q
C
Q
C
Q
C
Q
C
Q
C R Reset 11
Q
C R
Q
C
Q
C
Q
C
Q
C
Q4 = Pin 5 Q5 = Pin 3 Q6 = Pin 2
Q7 = Pin 4 Q8 = Pin 13 Q9 = Pin 12
VCC = Pin 16 GND = Pin 8
Figure 5. Expanded Logic Diagram
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MC74HC4040A
1 Clock Reset Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 2 4 8 16 32 64 128 256 512 1024 2048 4096
Figure 6. Timing Diagram
APPLICATIONS INFORMATION
Time-Base Generator
A 60Hz sinewave obtained through a 1.0 Megohm resistor connected directly to a standard 120 Vac power line is applied to the input of the MC54/74HC14A, Schmitt-trigger inverter. The HC14A squares-up the input waveform and
VCC 1/6 of HC14A 1.0M 20pF VCC
feeds the HC4040A. Selecting outputs Q5, Q10, Q11, and Q12 causes a reset every 3600 clocks. The HC20 decodes the counter outputs, produces a single (narrow) output pulse, and resets the binary counter. The resulting output frequency is 1.0 pulse/minute.
HC4040A Clock Q5
13 12 Q10 10 Q11 9 Q12 1/2 HC20 8
1 2 4 5
120Vac 60Hz
1/2 HC20
6
1.0 Pulse/Minute Output
Figure 7. Time-Base Generator
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MC74HC4040A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE R
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 10 0 10 0 0.020 0.040 1.01 0.51
B
1 8
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A -
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
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MC74HC4040A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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MC74HC4040A/D

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